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Asynchronous circuit
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#	Item
51	IGR Report GR/R16754/01 Behavioural Synthesis of Systems with Heterogeneous Timing (BESST) 1 Background/Context Add to Reading List Source URL: www.staff.ncl.ac.uk Language: English - Date: 2004-12-06 15:04:33 Electronic design automation Digital electronics Hardware description languages Electronic design Asynchronous circuit Logic synthesis Petri net Asynchronous system Verilog Electronic engineering Electrical engineering Electrical circuits
52	FINAL REPORT (GR/S81421/01) Add to Reading List Source URL: www.staff.ncl.ac.uk Language: English - Date: 2007-12-14 08:00:00 Digital electronics Integrated circuits Asynchronous circuit Logic synthesis Logic simulation Side channel attack High-level synthesis CPU design Integrated circuit design Electronic engineering Electronic design automation Electronic design
53	FINAL REPORT (GR/S12036) Synthesis and Testing of Low-Latency Asynchronous Circuits (STELLA) A.Yakovlev, A. Bystrov, A.M.Koelmans, G. Russell and D.J.Kinniment (School of Electrical, Electronic and Computer Engineering, Add to Reading List Source URL: www.staff.ncl.ac.uk Language: English - Date: 2006-06-07 13:42:56 Electrical circuits Electronic design Synchronization Asynchronous circuit Asynchronous system Digital electronics Logic synthesis CPU design VHDL Electronic engineering Electronic design automation Central processing unit
54	EPSRC Grant JOINT FINAL REPORT Add to Reading List Source URL: www.staff.ncl.ac.uk Language: English - Date: 2006-10-11 06:58:17 Electromagnetism Electronic design Synchronization Concurrency Asynchronous system Asynchronous circuit Petri net Digital electronics VHDL Electronic engineering Electrical circuits Electrical engineering
55	November 2008 Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks (SYRINGE) EP/C007298/1 Alex Yakovlev (Principal Investigator), Gordon Russell, David J.Kinniment, Newcastle University Add to Reading List Source URL: www.staff.ncl.ac.uk Language: English - Date: 2008-11-12 14:13:03 Electromagnetism Integrated circuits Electronic design automation Arbiter Asynchronous system Network On Chip Asynchronous circuit Digital electronics Synchronization Electronic engineering Electrical engineering Electrical circuits
56	Final Report on EPSRC grant “Self-Timed Event Processor” (EP/E044662/1) Prof. Alex Yakovlev and Dr Fei Xia, School of EECE, Newcastle University Main areas of achievement: (1) Foundations and basic modelling techniqu Add to Reading List Source URL: async.org.uk Language: English - Date: 2010-08-23 08:23:22 Electromagnetism Network On Chip Asynchronous circuit Yakovlev Arbiter Petri net Electronic engineering Electrical circuits Electrical engineering
57	November 2008 Next Generation of Interconnect Technology for Multiprocessor SoC (NEGUS) EP/C512812/1 A.Yakovlev (Principal Investigator), A. Bystrov, A. Koelmans, D.J. Kinniment, Newcastle University This three year proj Add to Reading List Source URL: www.staff.ncl.ac.uk Language: English - Date: 2008-11-24 05:50:27 Integrated circuits Electrical circuits Electronic design automation Network On Chip Asynchronous system Field-programmable gate array Advanced Learning and Research Institute Asynchronous circuit Yakovlev Electronic engineering Electrical engineering Electronics
58	Theme B: Energy Harvesting-Aware Computation Circuits Newcastle University and University of Southampton Prof Alex Yakovlev ([removed]), Prof Bashir Al-Hashimi, Dr Alex Bystrov, Dr Delong Shang, Dr Fei Xia Add to Reading List Source URL: async.org.uk Language: English - Date: 2013-04-29 09:20:35 Electrical circuits Clock signal Digital electronics Electronic design automation Asynchronous circuit Power gating Low-power electronics Energy harvesting Gating Electronic engineering Electrical engineering Electromagnetism
59	The ‘Asynchronous’ Bibliography B IB TEX database file async.bib Ad Peeters May 5, 2004 References Add to Reading List Source URL: www.win.tue.nl Language: English - Date: 2004-05-05 05:12:10 Electromagnetism Asynchronous system Asynchronous circuit Arbiter Sequential logic Delay insensitive circuit Robert Drost Kwabena Boahen Electrical circuits Electronic engineering Electrical engineering
60	One Billion Packet per Second Frame Processing Pipeline Mike Davies Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:21:45 Asynchronous circuit Clock signal Logic family IPv6 Futures and promises Dynamic logic Electrical engineering Electronic engineering Electrical circuits Computing

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